1. Field of the Invention
The present invention relates to a method for adjusting a tuning circuit and a receiver circuit.
2. Description of the Related Art
A high-frequency circuit employed in a receiver adopting a synthesizer method has a configuration like one shown in FIG. 10. As shown in the figure, broadcast signals received by an antenna 1 are supplied to an antenna tuning circuit 2 for selecting a signal SRX having the frequency of a desired broadcast. The antenna tuning circuit 2 supplies the selected signal SRX to a mixer circuit 5 by way of a high-frequency amplifier 3 and an inter-stage tuning circuit 4. In the mean time, a VCO (Voltage-Controlled Oscillator) 61 generates an oscillation signal SLO having a frequency determined in advance and supplies the signal SLO to the mixer circuit 5 as a local oscillation signal.
The antenna tuning circuit 2 is an alternating-current parallel circuit consisting of a tuning coil 2L and a variable-capacitance diode 2C. By the same token, the inter-stage tuning circuit 4 is an alternating-current parallel circuit consisting of a tuning coil 4L and a variable-capacitance diode 4C. A system control circuit 8 supplies digital tuning data D2 and D4 to a D/A conversion circuits 92 and 94 respectively. The D/A conversion circuit 92 coverts the digital tuning data D2 into an analog tuning voltage V2 and supplies the analog tuning voltage V2 to the variable-capacitance diode 2C in order to control the frequency of a signal generated by the antenna tuning circuit 2. By the same token, the D/A conversion circuit 94 coverts the digital tuning data D4 into an analog tuning voltage V4 and supplies the analog tuning voltage V4 to the variable-capacitance diode 4C in order to control the frequency of a signal generated by the inter-stage tuning circuit 4.
The VCO 61 is a portion of a PLL (Phase-Locked Loop) circuit 6. The VCO 61 also supplies the oscillation signal SLO generated thereby to a variable frequency division circuit 62 for generating a divided-frequency signal with a frequency 1/N times the frequency of the oscillation signal SLO, where notation N denotes a positive integer. The variable frequency division circuit 62 supplies the divided-frequency signal to a phase comparison circuit 63. In the mean time, a signal generation circuit 64 generates a signal having a reference frequency and supplies the reference-frequency signal to the phase comparison circuit 63.
The phase comparison circuit 63 compares the phase of the divided-frequency signal received from the variable frequency division circuit 62 with the phase of the reference-frequency signal received from the signal generation circuit 64 and supplies an output signal representing a difference in phase between the divided-frequency signal generated by the variable frequency division circuit 62 and the reference-frequency signal generated by the signal generation circuit 64 to a loop filter 65. The loop filter 65 extracts a DC voltage from the output signal received from the phase comparison circuit 63 and supplies the DC voltage to the VCO 61 as a voltage for controlling the oscillation frequency. The DC voltage has a level varying in accordance with the difference in phase between the divided-frequency signal generated by the variable frequency division circuit 62 and the reference-frequency signal generated by the signal generation circuit 64. Thus, since the frequency of the oscillation signal SLO generated by the VCO 61 is N times the reference frequency of a signal generated by the signal generation circuit 64, the frequency of the oscillation signal SLO generated by the mixer circuit 5 can be changed in accordance with control executed by the system control circuit 8 to vary the frequency-division rate N.
Receiving the oscillation signal SLO from the VCO 61 and the signal SRX of the desired broadcast from the inter-stage tuning circuit 4, the mixer circuit 5 converts the signal SRX into a signal SIF having an intermediate frequency and supplies the SIF to an intermediate-frequency circuit 7.
It is to be noted that, in this specification, the following references are used: Japanese Patent Laid-open No. 2003-037480 and Japanese Patent Laid-open No. 2006-287459.